Please use this identifier to cite or link to this item: 192.168.6.56/handle/123456789/58031
Title: Verification Methodology Manual for SystemVerilog
Authors: Janick, Bergeron
Issue Date: 2006
Publisher: Synopsys
URI: http://10.6.20.12:80/handle/123456789/58031
ISBN: 978-0-387-25538-5
Appears in Collections:Electrical and Computer Engineering

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