Please use this identifier to cite or link to this item: 192.168.6.56/handle/123456789/57998
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dc.contributor.authorVALERIA, BERTACCO-
dc.date.accessioned2019-03-26T08:22:47Z-
dc.date.available2019-03-26T08:22:47Z-
dc.date.issued2006-
dc.identifier.isbn0-387-2441 1-5-
dc.identifier.urihttp://10.6.20.12:80/handle/123456789/57998-
dc.language.isoenen_US
dc.publisherSpringer Science+Business Media, Inc.en_US
dc.titleSCALABLE HARDWARE VERIFICATION WITH SYMBOLIC SIMULATIONen_US
dc.typeBooken_US
Appears in Collections:Electrical and Computer Engineering

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