Title:	Fast, Efficient and Predictable Memory Accesses Optimization Algorithms for Memory Architecture Aware Compilation
Authors:	Wehmeyer, Lars
Keywords:	Fast, efficient and Predictable
Issue Date:	2006
Publisher:	Spriger
Description:	This work first presents an overview over the used timing, energy and simulation models for one processor architecture and for different memory architectures like caches, scratchpad memories and main memories in both SRAM, DRAM and Flash technology. Following an introduction to the used compilation framework, the compiler based exploitation of partitioned scratchpad memories is presented. A simple formalized Base model is presented that models the consequences of statically allocating instructions and data to several small scratchpad partitions, followed by a number of extensions that treat memory objects and their dependencies at a finer granularity. A method for allocating objects to separate scratchpad memories for instructions and data, as found in the most recent ARM designs, is also presented. Finally, a model that also considers the leakage power of memories is introduced. Results show that significant savings of up to 80% of the total energy can be achieved by using the presented scratchpad allocation algorithms. The flexibility and extensibility of the presented approaches is another benefit.
URI:	http://10.6.20.12:80/handle/123456789/39309
ISBN:	1-4020-4821-1
Appears in Collections:	Architecture

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