Logic and Architecture Synthesis

Please use this identifier to cite or link to this item: 192.168.6.56/handle/123456789/46710

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DC Field	Value	Language
dc.contributor.editor	Saucier, Gabriele	-
dc.date.accessioned	2019-02-22T07:20:51Z	-
dc.date.available	2019-02-22T07:20:51Z	-
dc.date.issued	1995	-
dc.identifier.isbn	978-0-387-34920-6	-
dc.identifier.uri	http://10.6.20.12:80/handle/123456789/46710	-
dc.description	In this book, we will focus on automatic design generation from a behavioral description, in other words, synthesis. Depending on the level of the behavioral input description, one is dealing with "logic synthesis" whose input consists of a set of boolean functions, "controller synthesis" based on a finite state machine input description, "RTL synthesis" starting from a Register Transfer Level description, "high level synthesis" which accepts an algorithmic description or "system level synthesis" which accepts a set of communicating processes as input. A typical design process starts with a higher level of synthesis and works down to logic synthesis producing an optimized structural specification of the circuit. This book, however, follows research topics in a chronological order and therefore starts with the lower level synthesis tasks, working its way up to system level synthesis.	en_US
dc.language.iso	en	en_US
dc.publisher	A catalogue record for this book is available from the British library	en_US
dc.subject	Architecture Synthesis	en_US
dc.title	Logic and Architecture Synthesis	en_US
dc.type	Book	en_US
Appears in Collections:	Architecture

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