Please use this identifier to cite or link to this item:
192.168.6.56/handle/123456789/2992
Title: | Tunnel Field-Effect Transistors (TFET) Modelling and Simulations |
Authors: | Jagadesh Kumar, Mamidala |
Keywords: | Tunnel Field-Effect Transistors ; Integrated Circuits ; Design and Construction |
Issue Date: | 2017 |
Publisher: | John Wiley & Sons |
URI: | http://10.6.20.12:80/handle/123456789/2992 |
ISBN: | 203 |
Appears in Collections: | Civil Engineering |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.